Entry-Level FPGA Design Engineer

North Logan, UT

Full Time

Civil and Commercial Space

Entry Level

Job ID: 9533
Date Posted: September 17, 2026

Space Dynamics Laboratory (SDL) is in search of a junior FPGA design engineer to assist with the design, fabrication, test and support of electronics for telecommunication hardware for space vehicles and sensor payloads in our CVS Division. The selected candidate will be involved in all aspects of payload algorithm discernment, development, optimization, and testing. The selected candidate must be able to work as part of larger electronics teams, internal and external to the organization, and own all aspects of their assigned block of the design from concept to integration and test.

The Civil & Commercial Space (CVS) Division is at the forefront of scientific research and space exploration. We equip major Government and commercial missions with calibrated state-of-the-art sensors and satellites. We also provide world-class AI&T technologies and mission management. Our projects include challenges across planetary science, Earth observation, heliophysics, and astrophysics. Be part of a team that pushes the boundaries of what’s possible in space and contributes to monumental scientific discoveries.

This position is full-time and is located in Logan, UT.

Required Qualifications:

Must be a U.S. citizen, lawful permanent resident of the U.S., or other U.S. Person
Bachelor’s degree in electrical and/or computer engineering
Should be comfortable with:
- Basic digital and analog circuits
- FPGA design
- Embedded software
- Ground support equipment
- Automated test scripting
- Experience with FPGA debugging tools and hardware troubleshooting equipment
- Experience with static timing analysis and timing closure
Hands-on testing and handling of space electronics in a laboratory environment

Desired Qualifications:

Expertise with digital communications
Expertise with CCD applications and supporting peripherals
Experience working on NASA (or other US government) funded projects
Master’s Degree

Salary Range

$90,000 - $140,000
- Salary commensurate on education and relevant experience

This range serves as a general guideline and may vary based on factors such as role, level, location, market conditions, and individual qualifications, including job-related skills, experience, and relevant education or training. The range displayed in the job advertisement reflects the minimum and maximum target salaries across all U.S. locations. Specific salary details for a candidate’s preferred location can be provided by the recruiter or HR manager during the hiring process.

Why Join SDL?
SDL offers competitive salaries and a comprehensive benefits package. Visit our Benefits Page to learn more about what we offer.

SDL delivers advanced multi-domain solutions to protect national security and enable scientific discovery. Our expertise in satellites, sensors and instruments, ground systems and data processing, and autonomous systems plays a critical role in missions supporting NASA and the Department of Defense. Join our team of engineers, scientists, technicians, and business professionals in our seventh decade of delivering mission success.

At SDL, we strive to uphold a culture of respect, collaboration, empowerment, and accountability. We listen with open minds, seek to understand diverse perspectives, and engage in thoughtful dialogue. We work together by sharing knowledge, involving others, and offering support. We trust and empower our team members to take ownership, act with integrity, and be accountable. Above all, we deliver on our commitments to each other and to our mission partners.

The application window for this position is expected to remain open for approximately 7 days; however, it may be shortened or extended depending on business needs and the availability of qualified candidates. We encourage interested candidates to submit their applications promptly.

For questions, assistance, or accommodation with the application process or the DoD SkillBridge program, please contact employment@sdl.usu.edu.

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Entry-Level FPGA Design Engineer

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